1. Field of the Invention
The present invention generally relates to interfacing high speed computer systems to other such systems and to personal computers used as terminals or workstations in a high speed computer system. The preferred embodiment of the invention is described in the environment of a standard High Performance Parallel Interface (HIPPI) as implemented on an IBM 3090 mainframe computer, an IBM PERSONAL SYSTEM/2 (PS/2) computer and an RISC SYSTEM/6000 computer, the latter two computers having the 32-bit MICRO CHANNEL bus; however, it will be understood that the invention can be adapted to other mainframe computers and other personal computers using different bus architectures. (PERSONAL SYSTEM/2, PS/2, RISC SYSTEM/6000, and MICRO CHANNEL are registered trademarks of IBM Corp.)
2. Description of the Prior Art
High performance personal computers based on the Intel i386 and i486 microprocessors, such as IBM's PERSONAL SYSTEM/2 (PS/2) computers, and reduced instruction set computer (RISC) microprocessors, such as IBM's RISC SYSTEM/6000 workstations, are making possible workstations with enhanced graphics capabilities. (i1386 and i486 are registered trademarks of Intel Corp.) The large memories addressable by these microprocessors using an operating system such as IBM's OPERATING SYSTEM/2 (OS/2) or AIX, IBM's licensed version of UNIX, allow for the rapid processing of the enormous quantity of data required to support, for example, three dimensional graphics. (OPERATING SYSTEM/2, OS/2 and AIX are registered trademarks of IBM Corp., and UNIX is a registered trademark of AT&T Corp.) While these computers are competent stand alone systems, the greatest potential for improved performance is to interconnect them with a high performance host system, such as IBM's 3090 system.
A high speed channel is a proposed standard that has been developed by the X3T9.3 Task Group of the American National Standards Institute (ANSI). The ANSI draft standard is X3T9/88-127, Rev. 6.7. This standard uses a four byte parallel bus to transmit information at a speed of 100 megabytes (MB) per second. IBM announced its version of a High Performance Parallel Interface for the 3090 system as a Super computer System Extension in May 1989. Transmission over the channel is controlled by several control signals. These signals permit the sender and the receiver to synchronize transfers properly. FIG. 1 shows the layout of the signals in a HIPPI connection. A full implementation of the channel uses two identical subchannels, one of inbound data and the other for outbound. The definition of the channel permits the two subchannels to operate simultaneously. For the purposes of the present invention, the channel operation can be summarized by describing the functions of signals that are used by the channel as shown in FIG. 1.
1. The request line is used by the source device (e.g., the 3090) to signal the destination (i.e., a workstation) that a channel transfer is desired. The destination responds by asserting the connect signal. PA0 2. Connect is asserted by the destination device in response to a request signal from the source. Connect remains active until either the request signal deactivates or the destination decides to break the connection. Connection is usually ended by the source dropping Request so deactivation of Connect for any other reason is usually due to a malfunction. Request and connect remain true during channel operations. PA0 3. The interconnect wires form a current loop from source to destination. By sensing the current flow in this loop, it can be determined that cables are connected between source and destination. PA0 4. Information is transferred on the data and parity wires of the interface. There are four bytes (32 bits) with a single parity bit for each byte for a total of 36 bits. PA0 5. The Ready signal is asserted by the destination to signal that it is ready to receive a burst of data. The sending of Ready signals is not interlocked to the transmission of bursts. The destination can send Ready "ahead of time" to avoid signaling delay. The source will count the number of Ready signals sent and continue transmission until the count is exhausted. PA0 6. The Packet signal is used by the source to identify a group of one or more bursts as a unit or packet. Packet is asserted by the source after the Request/Connect sequence and thus precedes the first burst. Packet is deactivated by the source after a fixed number of bursts have been transmitted. If count of Ready signals sent is not zero, the source will continue with the next packet immediately; otherwise, it will wait for a Ready signal. PA0 7. A burst of data on the channel contains 256 transfers, each of which contains one fullword (four bytes) of data. The data is transferred on the four byte data bus of the channel. The source sends a burst of data in response to the Ready signal sent by the destination. The source will send one burst for each ready signal sent by the destination. Note that the destination does not have to receive a burst before sending another Ready signal; it may signal Ready "ahead of time" when it has room to buffer the burst. If the Ready signal for a burst arrives at the source prior to the completion of the present burst, then the net burst will be transmitted without any delay. This feature permits the 100 MB rate to be sustained with large buffers. The burst line shown in FIG. 1 is made active when the first data word (HIPPI data word--4 bytes) is placed on the bus and remains active for the duration of the transfers. PA0 8. The Clock signal is generated by the source and is times such that it can be used by the destination to properly receive and latch up the data and control signals. This signal has a fixed period of 40 nanoseconds (ns). The clock signal runs continuously.
The HIPPI adapter as implemented by IBM is illustrated in FIG. 2. It consists of inbound and outbound sections 11 and 12, respectively, with essentially no interconnections between the two sides. The inbound side receives data from the HIPPI channel via receiver circuits 13 which convert the differential signals on the cable to single ended signals for the adapter logic. The received data is first captured in a latch 14 that is clocked using the inbound clock signal. Since the source controls the skew between the data and the clock signal, this technique ensures reliable capture of the data. Once the data is captured, it must then by synchronized with the local clock 16 in the adapter. The clock synchronizer circuitry 18 uses clock signals from the inbound HIPPI channel and the local clock 16 to perform this operation. The data is then transferred to a second latch 20 where it can be used by the logic of the adapter. The inbound side may also include optional logic 21 to decode routing information that is transmitted on the HIPPI channel during the connect sequence. This information, called the I-field, is placed on the data bus when the Request signal is asserted by the source. The I-field is simply a 32-bit number which can be used as desired to establish routing via switch devices. In the basic adapter implementation, this information is not needed but may be used like an address if desired. The ANSI standard does not define the format or interpretation of the I-field. On the outbound side of the adapter, the local clock 16 is used to transmit the data onto the HIPPI channel from a holding register 22. This register feeds differential driver circuits in the transmitter 24 which produce the proper signals for the interface. The local clock is sent out on the interface as the HIPPI clock since the adapter is the source for the outbound signals and must provide the clocking.
The HIPPI channel uses differential ECL (emitter coupled logic) drivers to achieve high performance. Because of this, it is not feasible to multidrop the channel if it is desired to attach more than one workstation to a channel. This restricts the HIPPI channel to a "two party" operation as shown in FIG. 3. If attachment to more devices is required, then a channel switch device must be inserted as shown in FIG. 4. The channel switch must have three sets of send and receive circuits as shown in FIG. 4. Another set of send and receive circuits must be added for each new device to be attached. In addition to the interface logic, the switch must implement internal switching functions which require that all of the HIPPI signals be available at each output. Since there are over forty signals in the interface, the complexity of the switch grows rapidly.
IBM's MICRO CHANNEL Architecture (MCA) bus was the first bus for personal computers providing 32-bit address and 32-bit data capabilities, replacing the former 24-bit addressing and 16-bit data standard. The MCA bus is available on certain models of IBM PS/2 and RISC System/6000 computers and on other licensed computers. Other 32-bit bus architectures are now on the market. At present, the maximum transfer rate to personal computers with a 32-bit bus architecture is limited to the speed of the host adapter devices which are currently available. The rate obtained depends on many factors, but it is usually less than one MB (megabyte) per second. In any case, the speed is limited to the speed of the block multiplexer channel on the host, which in the case of an IBM 3090 system is about 3 MB per second.